Exemplary embodiments relate to a semiconductor memory device and a method of reading the same and, more particularly, to a semiconductor memory device, which is capable of outputting correct data by changing a read voltage in response to interference resulting from neighboring memory cells, and a method of reading the same.
In a flash memory device, memory cells are coupled together in series such that neighboring memory cells share their sources and drains thereby forming a cell string. Further, a cell string may be coupled to a bit line. Each memory cell typically has a transistor structure in which a floating gate and a control gate are stacked. A memory cell array is directly formed within a P type well formed in a P type substrate or an N type substrate. The drain of a NAND cell is coupled to a bit line via a selected gate, and the source thereof is coupled to a source line via the selected gate. The control gates of the memory cells are consecutively arranged in a row direction and are coupled to a word line.
The operation of the NAND flash memory device is described below. A data program operation is performed starting from a memory cell which is the farthest from a bit line. High voltage Vpp is supplied to the control gate of a selected memory cell, and an intermediate voltage is supplied to the control gate and the selected gate of a memory cell placed closer to a bit line. 0 V or an intermediate voltage is supplied to the bit line in response to the value of data. When 0 V is supplied to the bit line, the corresponding voltage level is transferred to the drain of the selected memory cell, and electrons are then injected into the floating gate. Accordingly, the critical value of the selected memory cell shifts in the positive direction.
Recently, to further increase the degree of integration of flash memory devices, active research is being carried out on a multi-bit cell capable of storing plural data in a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
An MLC typically has two or more distributions of a threshold voltage and has two or more data storage states corresponding to the two or more distributions. An MLC capable of storing data of 2 bits has four data storage states (i.e., [11], [10], [00], and [01]). Distributions of the four data storage states correspond to distributions of a threshold voltage of the MLC.
For example, assuming that distributions of a threshold voltage of a memory cell are −2.7 V or less, 0.3 V to 0.7 V, 1.3 V to 1.7 V, and 2.3 V to 2.7 V, the data storage state [11] can correspond to −2.7 V or less, the data storage state [10] can correspond to 0.3 V to 0.7 V, the data storage state [00] can correspond to 1.3 V to 1.7 V, and the data storage state [01] can correspond to 2.3 V to 2.7 V. That is, if a distribution of the threshold voltage of the MLC corresponds to one of the four distributions of the threshold voltage, corresponding data information of 2 bits, from among the data storage states [11], [10], [00], and [01], is stored in the MLC.
As described above, the MLC has a number of distributions of a threshold voltage corresponding to the number of bits that can be stored. More specifically, an MLC capable of storing m bits has 2m distributions of a cell voltage.
FIG. 1 is a graph showing distributions of program threshold voltages of a known semiconductor memory device.
The program operation of a flash memory device of semiconductor memory devices is performed on a page basis. The pages are classified into even and odd pages, each sharing the same word line. In general, the program operation is first performed on the even page and then performed on the odd page.
Referring to FIG. 1, the program operation of a semiconductor memory device normally has a distribution A of a threshold voltage because of a program operation for an even page group. After the program operation is performed on an odd page group, the threshold voltage rises due to coupling with neighboring memory cells, thus shifting to a distribution B of the threshold voltage. Such a phenomenon is referred to as an interference phenomenon. The interference phenomenon is increased when the odd page group is programmed with a second state ‘state 2’ and a fourth state ‘state 4’ which have a greater shift of a threshold voltage than a first state ‘state 1’ and a third state ‘state 3’ which have a smaller shift of a threshold voltage.
If, as described above, the distribution of a threshold voltage rises, error can occur in a read operation for an even page group, thereby reducing reliability of the memory device.